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Where does read data go in a SRAM generator?
The read data is driven from the bit cell array through the column muxing and into the sense amp array. The OEb pin was used to determine whether the read data should be driven onto the data bus. This can enable multiple SRAM macros to be arranged on a distributed bus with only one SRAM driving that bus on any given cycle.
How are SRAM generators used in ASIC tools?
Similar to a standard-cell library, an SRAM generator must generate not just layout but also all of the necessary views to capture logical functionality, timing, geometry, and power usage. These views can then by used by the ASIC tools to produce a complete design which includes a mix of both standard cells and SRAM macros.
Is the SRAM generator based on a fake technology?
It requires gaining access to a specific fabrication technology, negotiating with a company which makes the SRAM generator, and usually signing multiple non-disclosure agreements. The OpenRAM memory generator is based on the same “fake” 45nm technology that we are using for the Nangate standard-cell library.
How do you get a SRAM generator for ECE?
Just as with standard-cell libraries, acquiring real SRAM generators is a complex and potentially expensive process. It requires gaining access to a specific fabrication technology, negotiating with a company which makes the SRAM generator, and usually signing multiple non-disclosure agreements.
Why was the OEB pin removed from openram?
The OEb pin was used to determine whether the read data should be driven onto the data bus. This can enable multiple SRAM macros to be arranged on a distributed bus with only one SRAM driving that bus on any given cycle. The OEb pin has since been removed in OpenRAM, and its functionality was tied to the CSb pin.
How many transistors are in a SRAM bitcell?
This is showing the netlist for one bitcell in the SRAM. This is a classic 6T SRAM bitcell with two cross-coupled inverters ( MM0, MM4 , MM1, MM5) and two access transistors ( MM2, MM3 ). Note that the transistors must be carefully sized to ensure correct operation of an SRAM bitcell!
What can you look at in openram memory generator?
You can look at the behavioral Verilog produced by the OpenRAM memory generator like this: