How to implement logic functions using only NAND OR NOR gates?
The core of this conundrum is as follows: The student has been presented with a Boolean Equation. He’s been instructed to create a corresponding truth table. He’s been told to perform Karnaugh map minimization. Finally, he must create an implementation using only NAND gates or only NOR gates.
How is an OR gate formed from a NAND gate?
With regard to the previous point, an AND gate is really formed from a NAND gate followed by a NOT gate (similarly, an OR gate consists of a NOR gate followed by a NOT gate). In addition to using 4 + 2 = 6 transistors, this means the AND gate (and an OR gate) consists of two stages of delay.
Can you do anything with just NAND gates?
So you can do anything with just NAND gates. Likewise, DeMorgan’s Theorem applies equally to NOR gates – invert the inputs and they become an AND gate. Typically, a logic IC will use either type as a basic building block, and repeat the gates as necessary.
What are the logical operations of conjunction and negation?
Abstract: The logical operations of conjunction, negation, and disjunction (alteration) are discussed with respect to their truth-table definitions.
Can a NAND gate be used instead of a NOR gate?
All of this means that if we can use a NAND or a NOR instead of an AND or an OR, then we can reduce our transistor count by a third. With regard to the previous point, an AND gate is really formed from a NAND gate followed by a NOT gate (similarly, an OR gate consists of a NOR gate followed by a NOT gate).
How to draw a circuit with only NAND gates?
De Morgan’s theorem can get confusing. You have (A*B)’ = A’+ B’. It may help to look at what this does to the schematic symbol. For the NAND gate it says change the symbol to an OR gate and move the bubbles to the input side. That being done, this circuit can be drawn;
Who are the DeMorgan transformations on NAND and NOR gates?
DeMorgan transformations on AND, OR, NAND, and NOR gates Augustus DeMorgan (1806-1871) was a contemporary of George Boole. DeMorgan made significant contributions to the field of symbolic logic; most notably, a set of rules we now call DeMorgan transformations.
How is the logical effort of a logic gate determined?
The logical effort is independent of the actual size of the logic gate, allowing one to postpone detailed calculations of transistor sizes until after the logical effort analysis is complete. Each logic gate is characterized by two quantities: its logical effort and its parasitic delay.