What is Xgmii interface?
10 gigabit media-independent interface (XGMII) is a standard defined in IEEE 802.3 designed for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board (PCB). It is now typically used for on-chip connections.
What is Xlaui interface?
From Wikipedia, the free encyclopedia. 10 Gigabit Attachment Unit Interface (XAUI /ˈzaʊi/ ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard.
What layer of OSI is Ethernet?
Data Link layer
A switch is a hardware device that works at layer 2 (the Data Link layer) of the OSI model. The Data Link layer is where the Ethernet protocol works.
Is MDIO open drain?
MDIO is open drain. Like you mentioned, during idle the line will go high to VDD.
What kind of Io standard does RGMII use?
To adhere to the RGMII specification we have reduced the IO voltage for the MIO bank to 2.7V and are using the LVCMOS25 IO standards from Vivado for the Gigabit Ethernet controller ports. But we are unable to detect the PHY connected using the MDIO interface.
Where is the RGMII interface on the FPGA?
RGMII Timing Basics. The RGMII interface is the physical connection between the Ethernet PHY and the Ethernet MAC. If you are using the Ethernet FMC, the PHY is the Marvell 88E1510, and the Ethernet MAC is inside the FPGA.
Is the RGMII interface compatible with lvcmos33?
The MIO banks are supplied with 3.3V. The incompatibility of the RGMII interface on Zynq PS with LVCMOS33 is discovered lately. But the ethernet PHY chip used on board supports 3.3V for the RGMII interface.
Which is Zynq controller uses the RGMII interface?
We are using Zynq xc7z020clg484-1 in a custom board. The Gigabit Ethernet controller of Zynq is used in our project and is assigned to the MIO pins with RGMII interface. The MIO banks are supplied with 3.3V. The incompatibility of the RGMII interface on Zynq PS with LVCMOS33 is discovered lately.