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How to deal with SOC metastability problems due to reset domain crossing?
In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will create an asynchronous crossing path and cause metastability at destination register.
How is clock domain crossing becoming more complex?
SoCs are becoming more complex these days. A lot of functionality is being added to chips and data is frequently transferred from one clock domain to another. Hence, clock domain crossing verification has become one of the major verification challenges in deep submicron designs.
When does metastability occur in a digital designer?
Metastability , therefore, can cause your logic to do some very unpredictable and (apparently) illogical things. For the digital designer, metastability can take place any time a signal crosses from one clock domain to another. This is called a “ Clock Domain Crossing ”, or CDC, and it needs some special engineering to be done properly.
When does clock domain crossing occur in a submicron?
Hence, clock domain crossing verification has become one of the major verification challenges in deep submicron designs. A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock.
When does a clock have a metastability problem?
Metastability problems commonly occur when a signal is transferred between circuitry in unrelated or asynchronous clock domains. The designer cannot guarantee that the signal will meet tSUand tHrequirements in this case, because the signal can arrive at any time relative to the destination clock.
When does a clock domain crossing take place?
So if that’s a clock domain, what’s a clock domain crossing? A clock domain crossing (CDC) takes place anytime the inputs to a given flip-flop were set based upon something other than the clock edge used by that flip-flop .