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How is the sine wave table generated in VHDL?
The values of the sine wave table are generated using the quantization_sgn VHDL function. In this function, the test on the positive or negative number is performed. In fact, for positive number the maximum possible value is 2^(NB-1)-1; for negative number the minimum possible value is -2^(NB-1) where NB is the number of quantization bit.
How is a sinusoidal DDS implemented in the VHDL?
The VHDL of the DDS implements a sine wave generator using an NCO 32 bit wide with programmable FCW and start phase. The sine LUT is generated using the initialization function “ init_lut_sin ”.
Is the mutual phase shift 180° in VHDL?
The mutual phase shift is 180°. In this post, we addressed the VHDL realization of a sinusoidal DDS. The VHDL code is fully synthesizable on FPGA and ASIC. By the way, using the approach of table computation using initialization function you must verify the correct implementation of the LUT on silicon.
How to generate transcendent function in VHDL code?
You can use the VHDL code above to generate all the transcendent function you need in your VHDL design simply modifying the function, number of bit for sample and quantization. In figure is reported the RTL view and post-layout report of the VHDL code for 1024 samples 8-bit data sine ROM, using Altera Quartus II
Can a 10 bit DAC generate a sine wave?
As clear, the 10-bit DAC can be driven either with SIN ROM output generating a sine wave or from the MSB of the NCO i.e. a programmable saw tooth. In this post relative to NCO, we dealt about the first step in DDS implementation i.e. the phase accumulator.
Can a FPGA implement a sine wave generator?
Note that you can use this code in your FPGA implementation since the synthesizer can initialize the LUT and implement a ROM with the sine sample as we will see in next in this section with an example using Altera Quartus II. The VHDL of the DDS implements a sine wave generator using an NCO 32 bit wide with programmable FCW and start phase.