What is a latch up condition?

What is a latch up condition?

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present.

What is latch up in physical design?

What is latch-up? A latch-up condition occurs within a design when an unintentional structure, which can be either a thyristor or a silicon-controlled rectifier (SCR) formed through the parasitic elements of the IC, is triggered and becomes locked (latched) into an on state [1].

What is latch up Explain Latch Up with cross section of a CMOS inverter How do you avoid latch up?

There are several ways to reduce the possibility of latchup:

1. Reduce the beta of either or both parasitic devices.
2. Increase well and substrate doping concentrations to reduce Rwell and Rsub.
3. Provide alternative (or better) collectors of the minority carriers.

How do you test for latch-up?

Latch-up Test It’s recommended to take the very first samples from the engineering lot or MPW run and send them to a Latch-up testing lab. The lab will apply the maximum possible supply power and then inject current to the chip inputs and outputs while measuring if a Latch-up occurs by monitoring the supply current.

What causes latch-up in an IGBT?

The description of latchup just presented is the so-called static latchup mode because it occurs when the continuous on-state current exceeds a critical value. Unfortunately, under dynamic conditions when the IGBT is switching from on to off, it may latch up at drain current values less than the static current value.

How well tap prevent latch up?

Well tap cells (or Tap cells) are used to prevent the latch-up issue in the CMOS design. Well tap cells connect the nwell to VDD and p-substrate to VSS in order to prevent the latch-up issue.

How do I stop my IGBT from latching?

The only way to turn off the IGBT in this situation is by forced commutation of the current, exactly the same as for a conventional thyristor. If latchup is not terminated quickly, the IGBT will be destroyed by the excessive power dissipation.

What happens when latch-up occurs in IGBT?

Explanation: Latch up occurs when the current through the device (Ic) collector current increases beyond a certain value. Explanation: Vce decreases from 0.9 to 0.1 of the initial value whereas others increase. Explanation: Due to its high gate impedance, IGBTs require less gate drive current.

How many latch up transistors does a jesd 17 have?

I am somewhat familiar with latchup (parasitic transistors in the body of a CMOS device that are activated by over- or under-voltage conditions). However, I have seen some devices that advertise “Latch-Up Performance Exceeds 250 mA Per JESD 17”, while others say “Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II”

What is the purpose of the IC latch up test?

This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria.

What is the MA value of a jesd 17?

However, I have seen some devices that advertise “Latch-Up Performance Exceeds 250 mA Per JESD 17”, while others say “Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II” What exactly does this mean? Specifically, what is the mA value in reference to?

Which is better jesd 78 or jesd 77?

I think the JESD 78 standard is newer, so is it also “better” despite having a lower mA rating? Both are standsrd tests defined by JEDEC, a member of the Electronic Industries Alliance ( EIA ).