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What is the advantage of dual slope ADC?
The dual-slope ADC has many advantages. Noise present on the input voltage is reduced by averaging. The value of the capacitor and conversion clock do not affect conversion accuracy, since they act equivalently on the up-slope and down-slope.
What is dual slope converter?
The dual slope ADC mainly consists of 5 blocks: Integrator, Comparator, Clock signal generator, Control logic and Counter. This input voltage is applied to an integrator. The output of the integrator is connected to one of the two inputs of the comparator and the other input of comparator is connected to ground.
Which type of a D converter is fastest?
flash ADC
The flash ADC is the fastest type available. A flash ADC uses comparators, one per voltage step, and a string of resistors. A 4-bit ADC will have 16 comparators, an 8-bit ADC will have 256 comparators.
What’s the difference between Delta Sigma and dual slope ADCs?
Comparing Types of ADCs Five main types of ADCs are commonly used: dual slope, successive approximation, flash, pipelined, and delta-sigma. The dual slope, used mostly in measurement instruments such as a digital voltmeter, has a slow sampling rate.
How are capacitors switched in a Sigma Delta converter?
Capacitors are rapidly switched (up to 10MHz) between the input, reference and ground as a function of the final output code. Each time these capacitors are switched to the ADC input, a current pulse is generated. A pattern of charging/discharging pulses is seen at the input pin of the ADC.
How is noise shaping used in Sigma Delta converter?
The second important technique that sigma-delta converters use is quantization noise shaping. The idea is to high-pass filter the quantization noise, so that the required oversampling ratio is reduced for a certain increase in resolution. A block diagram of a sigma-delta converter is shown in Figure 2.28.
What is full scale error of Sigma Delta converter?
Resistances up to 100k, combined with capacitors up to 10μF, may be placed in front of the ADC with less then 0.002% full-scale error (20ppm), while conventional ΔΣ ADCs with the same input network have greater than 10% full-scale errors (100,000ppm).