How DMA can cause cache coherence problem?

How DMA can cause cache coherence problem?

DMA transfers overcome the problem of occupying the CPU for the entire time it’s performing a transfer. DMA can lead to cache coherency problems If a CPU has a cache and external memory, then the data the DMA controller has access to (stored in RAM) may not be updated with the correct data stored in the cache.

What device looks after cache coherency?

cache controller
The whole process is controlled by a group of logic circuits called the cache controller. One of the cache controller’s main jobs is to look after ‘cache coherency’ which means ensuring that any changes written to main memory are reflected within the cache and vice versa.

What is DMA coherency?

Coherency is about ensuring all processors, or bus masters in the system see the same view of memory. Cache coherency means that all components have the same view of shared data. If that data were cached in the CPU and the DMA reads from external DDR, the DMA will read old, stale data.

How does cache coherence work?

In a shared memory multiprocessor with a separate cache memory for each processor, it is possible to have many copies of any one instruction operand: one copy in the main memory and one in each cache memory. When one copy of an operand is changed, the other copies of the operand must be changed also.

What are the main negative effects of DMA on cache memory?

Cache Coherency On processors with a data cache an unwanted side effect of using DMA is the possibility that the contents of the cache are no longer coherent with respect to main memory which can lead to data corruption problems.

What is the function of DMA?

Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data directly to or from the main memory, bypassing the CPU to speed up memory operations. The process is managed by a chip known as a DMA controller (DMAC).

What are the consequences of false sharing?

False sharing occurs when processors in a shared-memory parallel system make references to different data objects within the same coherence block (cache line or page), thereby inducing unnecessary coherence operations.

What is cache false sharing?

False sharing occurs when threads on different processors modify variables that reside on the same cache line. This invalidates the cache line and forces a memory update to maintain cache coherency. In Figure 1, threads 0 and 1 require variables that are adjacent in memory and reside on the same cache line.

What is DMA and its advantages?

Advantages: Transferring the data without the involvement of the processor will speed up the read-write task. DMA reduces the clock cycle requires to read or write a block of data. Implementing DMA also reduces the overhead of the processor.

How do you maintain cache coherency?

The following are the requirements for cache coherence: Write Propagation. Changes to the data in any cache must be propagated to other copies (of that cache line) in the peer caches. Transaction Serialization.

What are the problems in cache coherence?

The Cache Coherence Problem For example, the cache and the main memory may have inconsistent copies of the same object. As multiple processors operate in parallel, and independently multiple caches may possess different copies of the same memory block, this creates cache coherence problem.

What happens when a DMA controller has access to external memory?

DMA can lead to cache coherency problems If a CPU has a cache and external memory, then the data the DMA controller has access to (stored in RAM) may not be updated with the correct data stored in the cache.

Are there cache coherency anomalies in the DMA controller?

In some platforms, the processor and system DMA controller (or bus-master DMA adapters) exhibit cache coherency anomalies.

Why is it important to flush the cache before a DMA operation?

The following figure shows why it is important to flush the processor cache before a read or write operation using DMA if the host processor and DMA controller do not automatically maintain cache coherency. An asynchronous DMA read or write operation accesses data in memory, not in the processor cache.

Where does the data go after a DMA read?

An asynchronous DMA read or write operation accesses data in memory, not in the processor cache. Unless this cache has been flushed by calling KeFlushIoBuffers just before a read, the data transferred into system memory by the DMA operation could be overwritten with stale data if the processor cache is flushed later.