How do you cross a clock domain?

How do you cross a clock domain?

Common methods for synchronizing data between clock domains are:

1. Using m-FF based synchronizers.
2. Using MUX based synchronizers.
3. Using Handshake signals.
4. Using FIFOs (First In First Out memories).
5. Using Toggle synchronizers.
6. Using Xilinx specific clock domain crossing (CDC) tools.

What is the multi clock domain design?

The difference between the single clock domain and multiple clock domain designs is the phase difference between arrivals of the clock signals. The clock sources CLK1 and CLK2 are different for both the domains and regardless of the same or different frequencies the design is treated as multiple clock domain design.

What is clock domain crossing in VLSI?

In digital electronic design a clock domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary.

Are there any problems with clock domain crossing?

Several problems relate to passing a single bit between clock domains. Many of these issues and their potential solutions are documented in [3]. Before passing any signal between clock domains, fi rst register the signal in the sending clock domain.

How are multi-bit signals passed between clock domains?

The multi-bit signals are placed into a shared memory buffer (typically, a dual port RAM) from the sending clock domain and removed from the shared memory buffer in the receiving clock domain. Several applications require counter values to be passed between clock domains, such as FIFOs.

How to use clock domain crossing ( CDC ) techniques?

In Clock Domain Crossing (CDC) Techniques – Part 1, I briefly discussed metastability and two methods to safely synchronize a single bit. While those techniques are commonly used, in many applications we need to synchronize multiple control or data bits, like an encoded state or a data bus.

How is metastability controlled at clock domain crossing?

Another important technique used to pass signals between clock domains employs a multi-cycle path (MCP) formulation. For signals that traverse between clock domains, the effects of metastability must be localized and controlled at the crossing.