Contents
How to calculate the power consumption of a FPGA?
Due to the linear relationship between clock frequency and power consumption, data collected for the Spartan 3-E FPGA could be used to extrapolate its power consumption at 80MHz and make a direct comparison with CAP7 device. A value for percentage power reduction was calculated using the following formula:
Since static power consumption is directly related to gate-count, any FPGA larger than the one tested would consume more power and thus boost power advantage of the CAP7 MCU. Figure 2: Comparing the static power consumption of CAP7 and the Spartan 3-E FPGA. CAP7 reduces static power by 97%.
How does cap save power compared to FPGAs?
When compared to FPGAs, the power saved by using CAP is considerable: designers will see over a 95% reduction in static power, and nearly a 70% decrease in dynamic power. This power efficiency, coupled with CAP’s low NRE cost in comparison to ASICs presents a very attractive alternative to microcontroller-plus-FPGA designs.
Is the power consumption of FPGAs a necessary evil?
Long signal paths and inefficient clock-trees add to the power hungry nature of FPGAs—a necessary evil if one requires the ability to tweak their logic. Thus, FPGAs are natural choices for new product development. However, they are less than ideal once the logic is finalized and power issues become relevant.
When to switch to Intel FPGA power analyzer?
Intel recommends that you switch from the Intel® FPGA PTC to the Power Analyzer once your design is available. The Power Analyzer produces more accurate results because it has more detailed information about your design, including routing and configuration information about each of the resources in your design.
What is included in Intel FPGA standby power?
Standby power includes, but is not limited to, I/O and transceiver DC bias power. For Intel® Agilex™ devices, this power is included as part of the reported dynamic power. 2. Setting Up the Intel FPGA Power and Thermal Calculator 2.1. Availability