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What is the sensitivity list?
The sensitivity list is where you list all the signals that you want to cause the code in the process to be evaluated whenever it changes state. For example, clock or master reset is often used in a sensitivity list. Whenever the reset or clock changes state, the code inside the process is executed.
What happens if a signal is missing from the sensitivity list during synthesis?
If a signal is in the sensitivity list of a process, the process will “wake up” and be evaluated whenever the value of that signal changes. If it is not in the sensitivity list, a signal can change, but a process will not be re-evaluated to determine what the new outputs should be.
Is there a clock signal in the sensitivity list?
A clock signal in the sensitivity list is mandatory. One optional signal is accepted for implementing an asynchronous reset function. No other signals are permitted to (re-)activate the process. Skeleton of a safe and synthesizable process statement with memory. process (Clk_C, Rst_R) <——— sensitivity list, no more signals accepted!
How is the edge of a clock signal detected?
Hint: detecting an edge on a non-clock signal can frequently be done by sampling the signal in a shift register and comparing the sampled values at different stages of the shift register. Properly describing the detection of the edges of a clock signal is essential when modelling D-Flip-Flops (DFF).
Where does reset go on the sensitivity list?
Notice that reset is in the sensitivity list on the asynchronously resettable flop, but not on the synchronously resettable flop. Thus, the asynchronously resettable flop immediately responds to a rising edge on reset, but the synchronously resettable flop responds to reset only on the rising edge of the clock.
When must a signal be inserted into the sensitivity list of a process?
This is a common error (due to carelessness). Note that in VHDL 2008 you can use “all” keyword to automatically include all necessary signals in your process and avoid creating latches. For Synchronous Logic: Likely you only want your clock (and maybe your reset) signal in the sensitivity list.