Contents
What is time borrowing in Sta?
It is the property of latch, a path ending at a latch can borrow time from the next path in the pipeline such that the overall time of two paths remains the same. STA applies a concept of time borrowing for latch based designs.
What is arrival time and required time in Sta?
The arrival time of a signal is the time elapsed for a signal to arrive at a certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. To calculate the arrival time, delay calculation of all the components in the path will be required.
What is time stealing in VLSI?
Time Stealing can be used when a particular logic partition needs additional time. The additional time required should be deterministic at the time of the design and can adjust the clock phase of capture Flip Flop (FF2), so that data arrival time at the capture edge of FF2, will not violate setup.
What is latch timing?
The time before the clock falling edge that Data should remain stable is known as latch setup time. Similarly, the time after the clock falling edge that Data should remain stable is called latch hold time.
What is slack borrowing?
Time borrowing by definition is permitting logic to automatically use slack time from a previous cycle [1]. The key advantage of slack Page 2 borrowing is that it allows logic between cycle boundaries to use more than one clock cycle while satisfying the cycle time constraint [2].
What is the purpose of STA?
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations.
What is the concept of time borrowing in Sta?
STA applies a concept of time borrowing for latch based designs. Whatever data launched from Flip Flop1 at ons it should be reached to Flip Flop2 at next active edge i.e. 10ns (ideal case when setup hold time and skew and clock delay all are zero). If data reaches at Flip Flop2 after 10ns will not be able to capture the correct data.
How does time borrowing work in a latch?
Time borrowing concept in latches: It is the property of latch, a path ending at a latch can borrow time from the next path in the pipeline such that the overall time of two paths remains the same. STA applies a concept of time borrowing for latch based designs.
How does time borrowing in Sta-VLSI work?
Each stage is automatically borrow the time from the succeeding stages until we get the output. If the circuit made up of 4 flip flop instead of 4 latches, the 4 stage flip flop based design would consume a total of 28ns time but if we are using latch the delay has been reduced to 20ns.
How does time borrowing affect the Setup Setup?
In simple term-time borrowing is the technique in which a longer path takes to borrow the time from the next path of subsequent logic. Time borrowing typically affects the setup since time borrowing is slowing the data arrival time i.e. data arrival time is more.
https://www.youtube.com/watch?v=Q4T1U8YA7xY