Where is the address of an ISR stored in MSP430?

Where is the address of an ISR stored in MSP430?

The address of an ISR is defined in an interrupt vector. The MSP430 uses vectored interrupts where each ISR has its own vector stored in a vector table located at the end of program memory.

Why do I say UCA X txbuf in MSP430?

I say UCA x TXBUF because the bridge should be bidirectional, so it can either be UCA0TXBUF or UCA1TXBUF. My interrupt service routine is based on TI’s UART examples available in the MSP430Ware packages.

Can a msp430f5529 be used in UART mode?

I am attempting to program a sort of bridge between UCA0 and UCA1 in UART mode on the MSP430F5529 using the MSP-EXP430F5529LP development board. I am using an interrupt for receiving data but for transmitting I am just loading the UCAxTXBUF directly (no TX interrupts are enabled).

How is my interrupt service routine based on?

My interrupt service routine is based on TI’s UART examples available in the MSP430Ware packages. The examples use a busy wait inside the ISR to wait for the TX buffer to become available (UCTXIFG goes high) before loading UCAxTXBUF with the data.

Where to find timer interrupts in MSP430?

Select the upper file from ccs_base, and click on the marker at the left to show the included files. There you have to select the „msp430g2553.h“ file and double click on it to open the file. I use the MSP430G2553, so if you are using the 2452 for example please choose the „msp430g2452.h“ file.

What does ccr0 in MSP430 stand for?

That means if CCR0 (the value we set to 50000 before) is reached an Interrupt will be fired. At this Moment the code stops the normal execution and jumps to the Interrupt handler. If there where more than one Interrupt there is a priority that says what Interrupt will be handled first.

When to use P1.1 in MSP430?

Now for the new stuff: configuring P1.1 as an interrupt. On the MSP430, you can choose if an interrupt should happen when a GPIO goes from low-to-high, or high-to-low. The Port 1 Interrupt Edge Select register (P1IES) controls which edge an interrupt happens on.