Contents
Which digital logic family has the lowest propagation delay time?
Discussion Forum
| Que. | The digital logic family which has the lowest propagation delay time is |
|---|---|
| b. | TTL |
| c. | CMOS |
| d. | PMOS |
| Answer:ECL |
Which logic family dissipates the minimum power?
Detailed Solution
| Logic Family | Advantages |
|---|---|
| Complementary metal-oxide-semiconductor (CMOS) | 1. Lowest power consumption 2. Used in all microcomputer chips today. 3. Most common logic family. |
| Transistor-transistor logic (TTL) | 1. Earliest developed. 2. Most rugged. 3. Least susceptible to electrical damage. |
How is the propagation delay high to low calculated?
The propagation delay high to low (t pHL) is the delay when output switches from high-to-low, after input switches from low-to-high. The delay is usually calculated at 50% point of input-output switching, as shown in above figure.
How is the propagation delay of a CMOS inverter calculated?
Propagation Delay of CMOS inverter The propagation delay of a logic gate e.g. inverter is the difference in time (calculated at 50% of input-output transition), when output switches, after application of input. In the above figure, there are 4 timing parameters.
Why does a high drive strength cell reduce RC delay?
High drive strength cell indicates a cell having low ‘ON’ resistance. Due to low resistance, the time required to charge the output capacitance will be low, i.e. RC delay reduces. This technique is useful to fix setup violation where the delay needs to reduced.
How is the delay of a cell reduced?
The inverse (i.e. high ‘ON’ resistance) is useful for fixing hold violation, where the delay needs to increased. Another intelligent method, but a leaky one, to reduce the delay of cell is to swap high threshold voltage (Vt) cell with low Vt cell.