Why are there so many problems with I2C?

Why are there so many problems with I2C?

Each byte received by the master is followed by an ACKM (ack-ed by the master) EXCEPT for the last byte, in which case the master will not ACK it, causing a NAK to proceed the stop condition! To make this even harder, most I2C hardware peripherals will not allow you fine-grained control of whether the master will ACK or NAK.

How is I2C data represented in a packet format?

I2C data is not represented as a bit-stream, but rather a specific packet format with framing (start and stop conditions) preceded by an address, which encapsulates a sequence of 8-bit bytes, each followed by an ACK or NAK bit. The first byte is supposed to be the address, but right from the bat, you have to deal with the first special case.

What happens in the middle of an I2C transaction?

The result is that the slave thinks that it is in the middle of an I2C transaction and awaits the expected number of master clock pulses to complete the current transaction, but the master thinks that it should be creating a start condition on the bus.

How is the I2C bus designed to work?

Very often the peripheral will just blithely ack every byte that it reads from the slave regardless. The I2C bus is designed to be driven only through open-drain connections pulling the bus down, it is pulled up by a pair of pull-up resistors (one on the clock line and one on the data line).

What should I do if my I2C transaction fails?

This means that typically you will need to disable the peripheral, change the pins to GPIO mode and bit-bang the clocks you need out of the port, after which you need to re-initialize the I2C peripheral and try the next transaction, and if this fails then rinse and repeat the process until you succeed.

Are there any timeouts in the I2C protocol?

Since I2C is essentially transaction/packet based and it does not include timeouts in the specification (SMBUS does of course, but most slave sensors conform to I2C only) there is a real chance that you are going to reset your host processor (or bus master) in the middle of such a transaction.

Do you need VCC for an I2C monitor?

Often, external I2C devices (like I2C masters or monitors) must be provided with Vcc. Are appropriate termination resistances attached between SDA, SCL and Vcc? The voltage level on SDA and SCL must be Vcc as long as the bus is idle and drop near GND if shorted to GND.

What’s the low level voltage on the I2C bus?

Further diagnostics is possible with Vcc, SCL and SDA connected to an oscilloscope and/or an appropriate I2C monitor device: Are the high and low-level voltages on SDA and SCL correct during I2C transfers? The I2C standard defines the low-level threshold with 0.3 Vcc, the high-level threshold with 0.7 Vcc.

Do you have to read or write on I2C?

The presence of this bit implies that all transactions on I2C should be uni-directional, that is they must either read or write, but in practice, things are not that simple.

Can a I2C transaction be terminated while SCK is high?

Any I2C transaction in progress will be terminated if SDA changes while SCK is high. Any I2C device which will want to assert or release SDA must either do so at a time when it can be certain that SCK isn’t going to rise.

How to get the bus unstuck in I2C?

Often getting the bus “unstuck” is as simple as providing the slave device enough clocks to convince it that the last transaction is complete. Some slaves behave well and after clocking them 8 times and providing a NAK they will abort their current transaction.

How do I detect the I2C ack in FPGA?

The DAC’s datasheet mentioned a device connectivity test by looking for the ACK from the device. Having access only to a analog oscilloscope I quickly figured out that the DAC was quite likely not sending ACK’s, because the frame on the serial bus was only long enough for a single byte whereas I’d expect three consecutive bytes.

How to I2C understand of ACK and NAK?

I do not understand how to implement i2c coding for white box (ACK/NACK Bit) shown in image. master must check ACK or NAK from the slave as it is writing bytes. If it receives ACK, it continues to send the next byte . If it receives NAK, then it must stop transmission and issue a stoP condition.

Why is there no acknowledgement from I2C slave?

This may happen directly after the address byte or later during the data transfer stage. Possible reasons are: The I2C slave could not correctly interpret the data on SDA because the SDA high or low-level voltages do not reach its appropriate input thresholds.

Which is the 10 bit address in I2C?

The vendor could say 0x123 (and only 10 of the 12 bits implied are the 10-bit address), or they could include the prefix and specify it as 0xF223.